1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated semiconductor devices, and, more particularly, to methods and systems for testing and evaluating the metallization layers of a back-end-of-line (BEOL) metallization system and the pillar bumps that may be formed thereabove.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. In addition to an increase in the speed of operation due to reduced signal propagation times, reduced feature sizes allow an increase in the number of functional elements in the circuit in order to extend its functionality. Moreover, even as overall device sizes have dramatically decreased, the manufacturers of advanced semiconductor devices remain under constant pressure to reduce both costs and manufacturing times so as to remain economically competitive.
In the manufacture of many sophisticated integrated circuits, it is usually necessary to provide electrical connections between the various semiconductor chips making up a microelectronic device. Depending on the type of chip and the overall device design requirements, these electrical connections may be accomplished in a variety of ways, such as, for example, by wirebonding, tape automated bonding (TAB), flip-chip bonding, and the like. In recent years, the use of flip-chip technology, wherein semiconductor chips are attached to carrier substrates, or to other chips, by means of solder balls formed from so-called solder bumps, has become an important aspect of the semiconductor processing industry.
In flip-chip technology, solder balls are formed on a contact layer of at least one of the chips that is to be connected, such as, for example, on a dielectric passivation layer formed above the last metallization layer of a semiconductor chip that includes a plurality of integrated circuits. Similarly, adequately sized and appropriately located bond pads are formed on another chip, such as, for example, a carrier package substrate, such that each bond pad corresponds to a respective solder ball formed on the semiconductor chip. The two units, i.e., the semiconductor chip and carrier substrate, are then electrically connected by “flipping” the semiconductor chip, bringing the solder balls into physical contact with the bond pads, and performing a so-called Controlled Collapse Chip Connection (C4) solder bump “reflow” process at high-temperature, so that each solder ball on the semiconductor chip melts and bonds to a corresponding bond pad on the carrier substrate. Typically, hundreds of solder bumps may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern semiconductor chips that usually include complex circuitry, such as microprocessors, storage circuits, three-dimensional (3D) chips, and the like, and/or a plurality of integrated circuits forming a complete complex circuit system.
As semiconductor devices have gradually been reduced in size over successive design technology node generations, pillar bumps made up of more highly conductive materials, such as copper, gold, silver and/or alloys thereof, have replaced solder bumps in at least some flip-chip and 3D chip applications. Pillar bumps offer several advantages over more traditional solder bump connections, including higher interconnect densities, improved electrical and thermal performance, a greater standoff between the chip and the substrate, easier underfilling after the bonding operation, greater device reliability, and the like. During a typical high temperature C4 solder bump reflow process, solder bumps will generally collapse and spread out to some degree, thereby changing shape and size during the bonding process. Pillar bumps, on the other hand, which may only have relatively small solder caps for bonding to the corresponding bonding pads, substantially retain their shape and dimensional stability during the reflow process, due in most part to the higher melting temperatures of a typical pillar bump material, such as copper and the like, as compared to that of a typical solder material. This improvement in dimensional stability in turn permits the fabrication of pillar bumps based on much tighter bump pitches than would commonly be used for solder bumps, and an some cases much finer redistribution wiring patterns, thus leading to higher interconnect densities.
As noted above, pillar bumps sometimes have a small solder cap, which may be used to bond the pillar bumps to respective bond pads on a corresponding carrier substrate during a high temperature reflow process. Typically, the carrier substrate material is an organic laminate, which has a coefficient of thermal expansion (CTE) that may be on the order of anywhere from 4-8 times greater than that of the semiconductor chip, which, in many cases, is made up primarily of silicon and silicon-based materials. Accordingly, due to the CTE mismatch between the semiconductor chip and the carrier substrate (i.e., silicon vs. organic laminate), the carrier substrate will grow more than the semiconductor chip when exposed to the reflow temperature, and as a consequence, thermal interaction stresses will be imposed on the chip/substrate package as the package cools and the solder caps solidify. FIGS. 1a-1d, which schematically illustrate at least some of the possible chip packaging thermal interaction effects that may occur during this process, will now be described.
FIG. 1a schematically illustrates a chip package 100, which includes a carrier substrate 101 and a semiconductor chip 102. The semiconductor chip 102 typically includes a plurality of pillar bumps 103, which are formed above a metallization system 104 (see FIG. 1d) of the chip 102. In at least some cases, the pillar bumps 103 include solder caps 103C, which generally facilitate the bonding operation between the pillar bumps 103 and corresponding bond pads (not shown) on the carrier substrate 101. During the chip packaging assembly process, the semiconductor chip 102 is inverted, or “flipped,” and brought into contact the carrier substrate 101, after which the chip package 100 of FIG. 1a is exposed to a reflow process 120 at a reflow temperature that exceeds the melting temperature of the material making up the solder caps 103C. Depending on the specific solder alloy used to form the solder caps 103C, the reflow temperature may be upwards of 200°-265° C. During the reflow process 120, when the material of the solder caps 103C is in a liquid phase, both the carrier substrate 101 and the semiconductor chip 102 are able to thermally “grow” in a substantially unrestrained manner, based on the coefficient of thermal expansion of each respective component. As such, both the carrier substrate 101 and the semiconductor chip 102 remain in an essentially flat, non-deformed condition, although each will grow by a different amount due to their different CTE's.
FIG. 1b, on the other hand, schematically illustrates the chip package 100 during a cool-down phase, when a thermal interaction begins to take place between the carrier substrate 101 and the semiconductor chip 102. As the chip package 100 cools, the solder caps 103C solidify and mechanically join the pillar bumps 103 on the semiconductor chip 102 to the bond pads on the carrier package substrate 101. As the chip package 100 continues to cool after solder cap 103C solidification, the CTE mismatch between the materials of the carrier substrate 101 and the semiconductor chip 102 cause the substrate 101 to shrink at a greater rate than the chip 102. Typically, this difference in thermal expansion/contraction is accommodated by a combination of out-of-plane deformation of both the carrier substrate 101 and the semiconductor chip 102, and some amount of shear deformation of the pillar bumps 103. This out-of-plane deformation induces shear and bending forces 101F, 101M in the carrier substrate 101, as well as shear and bending forces 102F, 102M in the semiconductor chip 102. Other localized effects may occur in the semiconductor chip 102 in areas immediately surrounding the pillar bumps 103, as illustrated in FIG. 1d and described below.
FIG. 1c schematically illustrates a plan view of the semiconductor chip 102 of FIGS. 1a-1b. As shown in FIG. 1c, the semiconductor chip 102 has a center 102C located at the intersection of an first chip centerline 102X and a second chip centerline 102Y of the chip 102. Additionally, a plurality of pillar bumps 103 may be distributed over the surface of the semiconductor chip 102. It should be noted, however, that while the pillar bumps 103 shown in FIG. 1c are depicted as being randomly positioned, it should be appreciated that the relative positions of the pillar bumps 103 are illustrative only, as the bumps 103 may generally be distributed in a substantially uniform or homogeneous fashion, at least locally, over the surface of the semiconductor chip 102. Furthermore, the schematically depicted shear force 102F that may be induced in semiconductor chip 102 as a result of the thermal interaction between the chip 102 and the carrier substrate 101 (see, FIG. 1b) will generally be oriented from the periphery 102P of the semiconductor chip 102 toward, or in the general direction of, the center 102C, as indicated by the arrows shown in FIG. 1c. 
FIG. 1d schematically illustrates an area of the semiconductor chip 102 surrounding an individual pillar bump 103A after cool-down of the chip package 100. For simplicity, the semiconductor chip 102 has been inverted relative to the chip packaging configurations illustrated in FIGS. 1a-1b, and the carrier substrate 101 is not shown. Furthermore, only the uppermost metallization layers 104A, 104B and 104C of a metallization system 104 of the semiconductor chip 102 are shown in FIG. 1d, and any metallization layers below layer 104C, device layers, or substrate layers of the chip 102 have not been depicted. The semiconductor chip 102 may include a passivation layer 106 formed above the last metallization layer 104A, an underbump metallization (UBM) layer 105U formed in and above an opening in the passivation layer 106, and a pillar bump 103A formed above the UBM layer 105U. In some cases, the pillar bump 103A may facilitate the creation of an electrical connection between the carrier substrate 101 (not shown in FIG. 1d) and one or more semiconductor devices (not shown) formed in the device level (not shown) of the semiconductor chip 102. However, in other cases, the pillar bump 103A may be a “dummy bump” that does not provide an electrical connection to chip circuitry (not shown), but wherein the “dummy bump” is included so as to provide the substantially uniform or homogeneous bump distribution previously noted.
When the pillar bump 103A is intended to provide an electrical connection to chip circuitry (not shown in FIG. 1d), the UBM layer 105U and the pillar bump 103A may be formed above a bond pad 105, which may be used to facilitate an electrical connection to an underlying contact structure 107. Both the bond pad 105 and the contact structure 107 shown in FIG. 1d are outlined with dotted lines, indicating that these elements may or may not be present below the pillar bump 103A. As noted previously, the bond pad 105 (when present) may be in contact with the contact structure 107 so as to facilitate the electrical connection of the pillar bump 103A to an integrated circuit (not shown) formed in the device level (not shown) below the metallization system 104. For illustrative purposes only, the contact structure 107 (when present) may include, for example, a contact via 107B formed in the metallization layer 104B, a conductive line 107C and a contact via 107D in the metallization layer 104C, and the like, whereas other configurations may also be used.
As noted above, during the cool-down phase, the out-of-plane deformation of the chip package 100 that is caused by the thermal interaction of the semiconductor chip 102 and the carrier substrate 101 will typically induce shear and bending forces 102F, 102M in the chip 102. These shear and bending forces 102F, 102M will result in localized loads acting on each pillar bump 103, such as a shear load 103S, a tensile or uplift load 103T and bending moment 103M across the pillar bump 103A. However, since the material of the pillar bump 103 is, in general, very robust, and typically has a stiffness that exceeds that of at least some of the materials that make up the semiconductor chip 102—and in particular, the dielectric materials included in the metallization system 104—relatively little deformation energy will be absorbed by plastic deformation of the pillar bump 103A during the chip packaging thermal interaction. Instead, the majority of the loads 103S, 103T and 103M will be translated through the pillar bump 103A and into the metallization layers, such as layers 104A-104C, underlying the pillar bump 103A. These translated loads will generally have the highest magnitude in an area of the metallization system 104 that is below the edges 113 (shown in FIG. 1d as a dotted line) of the pillar bump 103A.
Under the conditions outlined above, highly localized stresses may develop in one or more of the metallization layers of the metallization system 104, such as a tensile stress 108T on one side of the pillar bump 103A and a compressive stress 108C on the opposite side of the pillar bump 103A. Furthermore, if the stresses 108T and/or 108C are of a high enough magnitude, a local failure of one or more of the metallization layers may occur below the pillar bump 103A. Typically, a failure of a given metallization layer having a substantially homogeneous material system will manifest as a delamination or a crack 109, and will normally occur where the loads are highest—i.e., near the edges 113 of the pillar bump 103A, as shown in FIG. 1d. In other cases, such as those utilizing a substantially inhomogeneous material system having locally varying fracture energies, the crack 109 may only occur in a single metallization layer, such as the layer 104C shown in FIG. 1d, whereas in other cases, and depending on many factors, the crack 109 may propagate either deeper or shallower into the underlying metallization system 104, e.g., spreading from one metallization layer to another.
Delamination failures and cracks, such as the crack 108, that may occur in a metallization layer below a pillar bump, such as the pillar bump 103A shown in FIG. 1d, are sometimes subject to premature failure, as the crack 108 may prevent the pillar bump 103A from making a good electrical connection to the contact structure 107 therebelow. However, since the delamination/crack defects described above do not occur until the chip packaging assembly stage of semiconductor chip manufacture, the defects will generally not be detectable until a final quality inspection is performed. In some cases, after the flip-chip operation has been completed, the chip package 100 may be subjected to acoustic testing, such as C-mode acoustic microscopy (CSAM). Cracks 109 that may be present in the metallization system 104 of the semiconductor chip 102 below the pillar bumps 103 will have a characteristic appearance during the CSAM inspection process that is recognizably different from that of pillar bumps 103 that do not have such cracks 109 therebelow. Such pillar bumps are sometimes referred to as “white bumps,” “white spots,” or “ghost bumps,” since this is how the difference in the acoustic signal in the CSAM images was first visualized. White bump defects may impose a costly downside to the overall chip manufacturing process, as they do not occur, and hence cannot be detected, until a significant material and manufacturing investment in the chip has already occurred. Furthermore, in those instances where the assembled chip package 100 is not subjected to CSAM inspection, undetected white bump defects may lead to reduced overall device reliability.
Additionally, the development and use of dielectric materials having a dielectric constant (or k-value) of approximately 3.5 or lower—which are often referred to as “low-k dielectric materials”—has led to an increased incidence of white bumps. Typically, low-k dielectric materials have lower mechanical strength, mechanical modulus, and adhesion strength than do some of the more commonly used dielectric materials having higher k-values, such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. As metallization systems utilize more, and sometimes thicker, metallization layers that are made up of low-k dielectric materials, there is a greater likelihood that the lower strength low-k materials will rupture when exposed to the loads that are imposed on the metallization layers underlying the pillar bumps, thus leading to delaminations and cracks—i.e., white bump defects. In particular, cracks tend to occur, or at least initiate, in the low-k metallization layers that are closest to the upper surface of the a semiconductor chip—i.e., closest to the last metallization layer—as the deformation energy is typically greatest near the upper surface, while in many cases decreasing in lower metallization levels. Furthermore, it appears that the type of white bump problems described above may sometimes even be further exacerbated in metallization layers comprised of ultra-low-k (ULK) materials having k-values of approximately 2.7 or lower, which in some cases may have even lower-strength mechanical properties than that of some low-k materials.
In some prior art semiconductor chips, the detrimental effects associated with white bump defects can sometimes be minimized by reducing the number of critical and/or sensitive circuit elements that are positioned in those areas of a metallization system that are below and/or adjacent to pillar bumps that are formed in those regions of a chip where white bumps are more likely to occur. For example, the size of a body—i.e., its length or width—is one factor that may have a significant influence on the total amount of thermal expansion that body undergoes when exposed to an elevated temperature. As such, the points of greatest thermal interaction—and commensurately highest out-of-plane loads—may occur in those areas of the semiconductor chip which are farthest from a neutral center, or centerline, of the chip, such as the periphery of the chip, such as the periphery 102P and in particular, those areas near the corners 102E of the chip (see, e.g., FIG. 1c). Accordingly, during the design and layout of a given semiconductor chip, it is sometimes feasible to position critical circuit elements and to route at least some conductive elements away from those areas of the chip that are typically exposed to greatest amount of differential thermal expansion between the semiconductor chip and the carrier substrate, e.g., near the edges and corners of the chip.
However, simply adjusting the layout of the various circuit elements as described above does not always address all of the problems that may often be related to white bumps, which can sometimes occur in regions of a semiconductor chip that would not normally be associated with the highest thermal interaction and out-of-plane loads. For example, in some cases, a certain area of a particular low-k or ULK material layer of a given back-end-of-line (BEOL) metallization system may display mechanical properties that are uncharacteristically lower than may normally be expected of that specific material. Such lower mechanical properties may be due to any one of several different factors, including variation and/or drifting in the material deposition parameters, cleanliness, contamination, and/or microscratching issues associated with a given tool or wafer, and the like. Furthermore, such adjusted layout configurations often tend to give up valuable chip real estate, which can sometimes limit the type of applications for which the resulting chips may be used.
Accordingly, and in view of the foregoing, there is a need to implement new strategies to address the design and manufacturing issues associated with the detrimental effects that white bump occurrences can often have on a semiconductor chip during the typical chip packaging operations. The present disclosure relates to various testing methods and mitigation strategies that are directed to avoiding, or at least minimizing, the effects of one or more of the problems identified above.